Reset control register 0
| CORE_RST | Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. |
| PERIPH_RST | Writing a one activates the reset. This bit is automatically cleared to 0 after three clock cycles. |
| MASTER_RST | Writing a one activates the reset. This bit is automatically cleared to 0 after three clock cycles. |
| RESERVED | Reserved |
| WWDT_RST | Writing a one to this bit has no effect. |
| CREG_RST | Writing a one to this bit has no effect. |
| RESERVED | Reserved |
| RESERVED | Reserved |
| BUS_RST | Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. Do not use during normal operation |
| SCU_RST | Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. |
| RESERVED | Reserved |
| RESERVED | Reserved |
| M0_SUB_RST | Writing a one activates the reset. Writing a 0 clears the reset. This bit must be cleared by software. |
| M4_RST | Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. |
| RESERVED | Reserved |
| RESERVED | Reserved |
| LCD_RST | Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. |
| USB0_RST | Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. |
| USB1_RST | Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. |
| DMA_RST | Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. |
| SDIO_RST | Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. |
| EMC_RST | Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. |
| ETHERNET_RST | Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. |
| RESERVED | Reserved |
| RESERVED | Reserved |
| FLASHA_RST | Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. |
| RESERVED | Reserved |
| EEPROM_RST | Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. |
| GPIO_RST | Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. |
| FLASHB_RST | Writing a one activates the reset. This bit is automatically cleared to 0 after one clock cycle. |
| RESERVED | Reserved |
| RESERVED | Reserved |